1. Field of the Invention
The present invention relates to a semiconductor device and, particularly, to a MOS type transistor structure and a method of fabricating the same.
2. Description of the Related Art
With the ongoing miniaturization of transistors, an improvement in operating speed has been proposed. Recently, a MOS type transistor having a gate length of 0.25 .mu.m or smaller was developed. However, in contrast to such a shortened gate length, 1) the contact size, 2) the distance between the contact and gate, and 3) the distance between the contact and an element separating insulating film cannot be reduced correspondingly, and it becomes difficult to reduce the area of the source and drain diffusion layers. As a result, the ratio of the charge/discharge time of the source and drain diffusion layer capacitance to the operating speed of the transistor becomes larger, and this prevents an increase in the operating speed of the device. A method for solving this problem is proposed by Imai et al., 0.15 .mu.m Delta-doped CMOS with On-field Source/Drain Contacts, 1996 Symposium on VLSI Technology Digest of Technical Papers, Jun. 11-13, 1996/Honolulu, pgs. 172-173.
The structure of a MOS transistor according to Imai et al. and a fabrication method thereof is briefly described below with reference to the drawings.
First, the structure of the MOS transistor according to the related art is described by utilizing the plan layout of FIG. 6(a) and the cross sectional structure of FIG. 6(b).
As shown in FIG. 6(b), the structure of the MOS transistor according to the related art includes, on a silicon substrate of a first conductivity type, a well region 7 of the first conductivity type or a conductivity type opposite to the first conductivity type. On a surface of a portion of the silicon substrate 1 in which the well region 7 is formed, MOS transistors are formed which are electrically separated by an element separating insulating film 2.
On the surface of the portion of the silicon substrate 1 in which the well region 7 is formed, there is a selective silicon epitaxial layer 5 and a gate oxide film 9 on which a gate electrode 10 is formed.
An LDD side wall 12 and a TiSi (titanium silicide) layer 14 are formed on a side surface and an upper surface of the gate electrode 10, respectively.
The selective silicon epitaxial layer 5 is connected to a first polysilicon layer 4 and a selective polysilicon layer 6 which are formed in lamination, and these layers form a channel dope layer 8, a LDD (lightly doped drain) region 11 and source and drain regions 13 of the MOS transistor, respectively.
Furthermore, the channel dope layer 8 is formed immediately below the gate electrode 10, the LDD region 11 is formed immediately below the LDD side wall 12, and the source and drain regions 13 are formed between an outside of the LDD side wall and the element separating insulating film.
Furthermore, a TiSi layer 14 is formed on a surface of the selective polysilicon layer 6, an inter-layer insulating film 15 is formed on a whole surface of the wafer substrate, and contacts provided therein are connected to the source and drain electrodes as lead electrodes 16 of the source and drain, respectively.
FIGS. 7(a)-7(c), 8(a)-8(c) and 9(a)-9(c) show the steps of fabricating the MOS transistor according to the related art.
First, as shown in FIG. 7(a), an insulating film 2 for separating elements is formed on the silicon substrate 1 and, then, a silicon oxide film 3 having thickness of 5-20 nm is formed thereon. Furthermore, a first polysilicon layer 4 having thickness of 50-100 nm is grown on the whole surface of the substrate.
Then, as shown in FIG. 7(b), the first polysilicon layer 4 is patterned by a photolithographic technique. In this case, the first polysilicon layer 4 is patterned on the element separating insulating film 2 such that it is adjacent to the source and drain regions along the element region in which the transistor is formed with the element separating oxide film 2 and in parallel (same distance) to the gate electrode 10, as shown in the plan view in FIG. 9(b). In this case, an edge of the first polysilicon layer 4 is set 0-0.1 .mu.m inside the edge of the element separating insulating film 2. Also, the silicon oxide film 3 functions as a stopper in etching the first polysilicon layer 4.
Then, as shown in the cross section in FIG. 8(a) and the plan view in FIG. 8(b), after the silicon oxide film 3 is removed using, for example, a wet etching liquid, a silicon epitaxial layer 5 is selectively grown on the exposed surface of the silicon substrate 1. The thickness of the silicon epitaxial layer 5 is 30-100 nm. Simultaneously therewith, a selective polysilicon layer 6 is grown on the surface and periphery of the first polysilicon layer 4. The thickness of the selective polysilicon layer 6 grown on the first polysilicon layer 4 is on the order of 1/2 to 1/4 the thickness of the silicon epitaxial layer 5. The reason for this is that the surface of the silicon substrate is a &lt;100&gt; plane. On the other hand, a &lt;111&gt; plane orientation is predominant for polysilicon, and silicon grows slower in a &lt;111&gt; plane as compared to a &lt;100&gt; plane. The silicon epitaxial layer 5 selectively grown on the surface of the silicon substrate 1 can be connected to the side surface of the first polysilicon layer 4 and the selective polysilicon layer 6.
Then, as shown in FIG. 8(c), a well region 7 is formed by ion implantation using photoresist 17 as a mask and, thereafter, a channel dope layer 8 is formed by ion implantation to achieve a threshold value control. Then, as shown in FIG. 9(a), after a gate oxide film 9 having a thickness of 3-10 nm is formed on the surfaces of the silicon epitaxial layer 5 and the selective silicon layer 6, a polysilicon gate electrode 10 having a thickness of 10-20 nm is formed on the gate oxide film 9. In this case, the distance between the gate electrode 10 and the element separating insulating film 2 is set on the order of 0.05-0.4 .mu.m, as shown in the plan view in FIG. 9(b).
Then, as shown in FIG. 9(c), after an LDD region 11 is formed by implanting an impurity at low concentration, a side wall 12 is formed on the side surface of the gate electrode and, after the source and drain regions are formed by ion implantation, the source and drain regions 13 are activated by heat treatment. Thereafter, as shown in FIG. 6(b), a silicide film, in this case, a TiSi film, is formed by sputtering and, after sintering, the surface of the gate electrode 10, the surfaces of the selective polysilicon layer 6 and the surface of the first polysilicon layer 4 located below the selective polysilicon layer 6 and the surface of the source and drain regions 13 are silicided. Then, after an inter-layer insulating film 15 is formed and opened, the MOS type transistor is completed by forming the respective lead electrodes 16 through the openings.
In FIG. 8(a) which shows the embodiment of the related art mentioned above, in growing the silicon epitaxial layer 5 selectively on the surface of the silicon substrate 1, the selective polysilicon layer 6 grown on the surface of the first polysilicon layer 4 and covering the first polysilicon layer 4 may have an overhanging cross section as shown in FIG. 10. In forming the source and drain regions 13 by implanting an impurity at a high concentration (e.g., at a dose of about 1.times.10.sup.16 /cm.sup.2), a high resistance region 11A may occur because the ion implantation is partially blocked by the overhanging structure. The resulting transistor characteristics are degraded as shown in FIG. 11(a) due to the high resistance of this region.